1. Field of the Invention
This invention relates to integrated circuits (ICs). More particularly, it relates to a design technique and method to better protect electrical circuits such as an integrated circuit from electrostatic discharge (ESD) damage.
2. Background of Related Art
Electro-static discharge (ESD) is a potentially harmful high voltage spike of electricity that can be catastrophic to one or all integrated circuits (ICs) in an electronic device. Many will appreciate the spark that occurs between ones finger and a metal object after shuffling ones feet across a wool rug.
The possibility of ESD exposure has been accommodated in many conventional integrated circuits (ICs). For instance, signal pins of an ICs are protected by diodes or snapback devices in such a way that the ESD protection device is turned off during normal use of the ICs, but during a static discharge event the ESD protection turns on and provides a current path to ground for the static discharge. Power and ground pins are protected by power clamps which could use a snapback device or a MOSFET between power and ground to protect the IC during electrostatic discharges. A MOSFET based power clamp typically uses a triggering circuit to turn on (trigger) the MOSFET during an electrostatic discharge. By choosing an appropriate triggering circuit, the MOSFET based power clamp could turn on at a much lower voltage than a snapback based power clamp during an ESD event. Thus providing better protection to the ICs against electrostatic discharge.
There are three prevalent general approaches to the design of the triggering circuit for the MOSFET based power clamp. A first approach uses a circuit to detect the voltage level of the power rail, and triggers a power clamp when the voltage level is higher than the normal power supply voltage by a certain amount (e.g., when higher than 25%).
A main disadvantage in conventional power clamp technologies is that the circuit must be designed such that the power clamp must not turn ON during normal operation, otherwise it will lock up the IC. Because of this, the triggering voltage is conventionally set to be much higher than the normal power supply voltage, e.g., 30% higher than the normal power supply voltage. This solution is somewhat ineffective to fully protect against an ESD event.
A second approach is to trigger the power clamp by detecting a voltage surge, or transient, controlling a signal to the base of the MOSFET device. A typical transient triggered MOSFET based power clamp is taught by Merril and Issaq, “ESD Design Methodology,” EOS/ESD Symposium Proceedings (1993).
While this trigger method has the advantage of a low triggering voltage and hence providing better ESD protection to the IC, it is determined by the present inventors not to be able to clearly distinguish an ESD pulse from the normal power up of a circuit. For instance, a conventional MOSFET based power clamp will likely short the power supply to ground during normal power up of the circuit for a short duration determined by a relevant RC value input to the gate, which is typically set to around 2 to 5 microseconds (uS). Moreover, as the size of the integrated circuit (IC) chip grows, so must the number of power clamps on the chip. As this happens, it then becomes even more dangerous to allow the power clamp(s) to short the power supply to ground for even a few microseconds.
For example, in “hot swap” or “hot plug” applications where a circuit board or even just an integrated circuit (IC) are plugged into a powered system, too many power clamps shorting the power supply to ground could bring the entire system down.
A third conventional predominant approach to protecting an IC from the dangers of electro-static discharge (ESD) uses a circuit to detect the rise time (slew rate) of a triggering pulse, which in turn activates an ESD protection circuit.
It is conventionally assumed that ESD voltage pulses rise much faster than the rise in voltage on the power rail of a normal power supply power ON. In this conventional solution, power clamps are designed to turn ON only if the slew rate is higher than a given predetermined rate, so as to distinguish a normal power ON situation from an ESD voltage pulse. This is discussed, e.g., in Stockinger, et al., “Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies,” EOS/ESD Symposium Proceedings (2003).
The disadvantage in this conventional methodology is that it assumes that the slew rate of the relevant power supply is slow. However, in some applications such as in a hot-plug application where a plug is connected to a socket of a powered device, the slew rate of the power supply can be very fast. This renders the second approach somewhat ineffective to fully protect against many ESD events.
There is a need to accommodate and improve upon the current designs to avoid the danger of electro-static discharge exposure in an integrated circuit (IC) or functionally similar device.